FIGS. 1a and 1b illustrate an equivalent circuit of a conventional memory device formed from an array comprising a plurality of thermally assisted switching magnetic random access memory (TAS-MRAM) cells 1. Four such TAS-MRAM cells 1 are represented in FIGS. 1a and 1b. 
Each TAS-MRAM cell 1 comprises a magnetic tunnel junction represented by the numeral 2 in FIGS. 1a and 1b, and a select transistor 3, electrically connected to the magnetic tunnel junction 2. Although not represented in the FIGS. 1a and 1b, the magnetic tunnel junction 2 can be formed of a reference layer having a fixed magnetization, a storage layer having a direction that can be switched from a first stable direction to a second stable direction upon writing of the cell, and an insulating layer between the storage layer and the sense layer. The magnetic tunnel junction 2 can further comprise a first antiferromagnetic layer (not shown) pinning the magnetization of the reference layer and providing the fixed magnetization of the reference layer and a second antiferromagnetic layer (also not shown) pinning the storage layer when the magnetic tunnel junction 2 is at a temperature that is below a critical temperature of the second antiferromagnetic layer.
The array comprises a plurality of bit lines BL and a word lines WL, each bit line BL and each word line WL addressing a row and a column of the array, respectively. More particularly, the bit lines BL and word lines WL are electrically connected to the drain and gate of the select transistor 3, respectively. In the arrangement of FIGS. 1a and 1b, the source of the select transistors 3 are grounded through a plurality of source lines SL connected to rows of TAS-MRAM cells 1 of the array.
During a write operation (FIG. 1a) one of the TAS-MRAM cells 1 is selectively written by supplying a maximum voltage VddBL to one of the bit lines BL, and supplying a maximum voltage VddWL to one of the word lines WL. The selected TAS-MRAM cell 1, lying at the intersection of the activated bit line BL and word line WL, is shown encircled in FIG. 1a. The respective values of VddBL and VddWL are determined by the specifications of the select transistor 3.
More particularly, during the write operation, the select transistor 3 of the selected TAS-MRAM cell 1 is in a passing mode by applying the voltage VddWL to its gate, via the word line WL. The voltage VddBL applied on the bit line BL results in a voltage of VDS=Vdd−Vmtj at the drain of the select transistor 3, where Vmtj is the write bias voltage across the magnetic tunnel junction 2. The write bias voltage Vmtj must be high enough to pass a heating current 31 through the magnetic tunnel junction 2 capable of heating the TAS-MRAM cell 1 above the critical temperature of the antiferromagnetic layer in order to free the magnetization of the storage layer. During heating of the TAS-MRAM cell 1, means of switching the magnetization of the storage layer are applied.
Means of switching can comprise a magnetic field generated by a field current (not shown) passing through field lines (also not represented). Means of switching can also comprise passing a spin transfer torque current (not shown) through the magnetic tunnel junction 2, via the activated bit line BL, the storage layer magnetization being then switched by the so-called spin transfer torque (STT) effect.
After the storage layer magnetization has been switched, the select transistor 3 can be set in a blocked mode by deselecting the activated word line WL or bit line BL, causing the magnetic tunnel junction 2 to cool down below the critical temperature, where the storage layer magnetization is “frozen” in the written direction.
During a read operation represented in FIG. 1b, the select transistor 3 of the selected TAS-MRAM cell 1 (shown encircled in FIG. 1b) is set in a passing mode by applying a voltage VDD to its gate, via the word line WL. A relatively low read bias voltage VR, of about 300 mV, is applied to the magnetic tunnel junction 2, via the bit line BL, in order to pass a sense current 32 through the magnetic tunnel junction 2. The sense current 32 allows for measuring a junction resistance R of the magnetic tunnel junction 2, which value corresponds to the written direction of the reference layer magnetization relative to the magnetization of the reference layer.
During the write operation, the write bias voltage Vmtj is typically equal or greater than 1 V, its value being primarily limited by the breakdown voltage of the magnetic tunnel junction 2. When sinking the corresponding heating current 31, the select transistor 3 operates in its linear region. Since the select transistor 3 is operating below its saturation region, sinking the large heating current 31 requires the select transistor 3 to have a large size. Consequently, the size of the TAS-MRAM cell 1 becomes dominated by the size of the select transistor 3.